This invention relates to MNOS memory transistors and in particular to a technique for manufacturing radiation hardened drain source protected memory transistors using a redeposited silicon nitride gate dielectric.
The conventional drain source protected memory transistor has a deposited nitride layer that overlaps thick oxide protected non-memory regions. The thickness of the nitride layer and the charge at the nitride thick oxide interface both affect the threshold of the non-memory region. Since the operating characteristics of the drain source protected memory transistor depend on both memory and non-memory characteristics it is desirable to have independent control of their processing parameters.
The conventional MNOS memory transistor also exhibits positive charge buildup in its silicon dioxide layer when subjected to X-ray irradiation. The charge buildup results in a turn-on voltage shift that substantially degrades the transistor performance.
The present invention is directed toward providing an MNOS memory transistor that is impervious to the effects of any ionizing total dose irradiation and that also allows the threshold and operating characteristics of the non-memory and memory regions to be individually controlled.